University of California Portfolio Circuits Electrical Engineering Questions
I Have a 4 part Question help about my Circuit portfolio assignment. I just need help with designing circuits on Multisim which is a software that we use to draw the circuits and take pictures of.
1st Part – Design a circuit that implements the function, F(W,X,Y,Z) = ?m(2,6,8,11,14) as a NOR-OR, 2-level gate array. Submit the schematic and a screenshot of a simulation verifying the output for the input 1001.
2nd Part – Design a circuit that uses multiplexors to perform 1’s complement on a 3-bit binary number. Assume overflow bits are lost. Submit your schematic and a screenshot of a simulation verifying the output for an input of 110.
3rd part – Given four inputs, A,B,C,D, implement the following functions in a programmable array logic (PAL) circuit. Write the programming table and draw the circuit.
F1(A,B,C,D) = AB’ + A’C’D + CD
F2(A,B,C,D) = BCD + AD’
F3(A,B,C,D) = B’D + AD’ + AB’C’D + BCD
F4(A,B,C,D) = C+ AC’D’
4th part – A circuit that accepts two 1-bit binary inputs, A and B, adds A and B together and produces the outputs Sum and Carry is sometimes referred to as a “Half Adder”. Design a circuit that accepts inputs A, B and Opp and uses a multiplexor to select between a half-adder circuit (A+B) and a multiplier (A*B). Your outputs should be Sum and Carry. Submit two simulations of your Multisim schematic, one verifying the conditions A = 1, B = 1, Opp = 0 and the second verifying the conditions A = 0, B = 1, Opp = 1.